Biasing scheme for power amplifiers

ABSTRACT

A front-end module comprises a bias network including a current mirror, a junction temperature sensor, an n-bit analog-to-digital converter, an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions, and a power amplifier. The bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.16/802,177 filed Feb. 26, 2020 and entitled “BIASING SCHEME FOR POWERAMPLIFIERS,” which claims priority to U.S. Provisional Application No.62/810,853 filed Feb. 26, 2019, entitled “BIASING SCHEME FOR POWERAMPLIFIERS,” each of which is expressly incorporated by reference hereinin its entirety for all purposes.

BACKGROUND Field

The present disclosure relates to power amplifier circuits, relateddevices, and related methods for radio-frequency (RF) applications.

Description of the Related Art

Some power amplifier circuits include integrated duplex filters. Often,duplex filters and/or other components of power amplifier circuits canbe sensitive to damage from various factors such as process variationand temperature in such a way as to decrease the overall performance ofthe circuit.

SUMMARY

In accordance with some implementations, the present disclosure relatesto a front-end module comprising a bias network including a currentmirror, a junction temperature sensor, an n-bit analog-to-digitalconverter, an n-bit current source bank configured to automatically setreference current levels for one or more operating temperature regions,and a power amplifier. The bias network, junction temperature sensor,n-bit analog-to-digital converter, n-bit current source bank, and poweramplifier are integrated on a first semiconductor die.

The bias network may include a hybrid bias current topology of constantand proportional to square of temperature (PTAT2) current generators. Insome embodiments, the bias network includes a multi-stacked topology.The power amplifier may be a Silicon-On-Insulator (SOI) complementarymetal-oxide-semiconductor (CMOS) power amplifier. In some embodiments,the power amplifier is configured to provide an output power of at least22 dBm. The power amplifier may include an n-channel metal-oxidefield-effect transistor (NMOSFET).

In some embodiments, the power amplifier is configured to provide a gainflatness of less than 1 dB over a temperature range of −40° C. to 125°C. The power amplifier may be configured to operate at a first levelduring transmit modes and operate at a second level during non-transmitmodes. In some embodiments, the n-bit current source bank is configuredto set reference current levels for without feedback loops. The one ormore temperature regions may include 2^(n)+2 temperature regions. Insome embodiments, the n-bit current source bank is a proportional toabsolute temperature (PTAT) current source bank. The current mirror maybe a sub-threshold region current mirror.

In some teachings, the present disclosure relates to a semiconductor diecomprising a bias network including a current mirror, a junctiontemperature sensor, an n-bit analog-to-digital converter, an n-bitcurrent source bank configured to automatically set reference currentlevels for one or more operating temperature regions, and a poweramplifier.

The bias network may include a hybrid bias current topology of constantand proportional to square of temperature (PTAT2) current generators. Insome embodiments, the bias network includes a multi-stacked topology.The power amplifier may be a Silicon-On-Insulator (SOI) complementarymetal-oxide-semiconductor (CMOS) power amplifier. In some embodiments,the power amplifier includes an n-channel metal-oxide field-effecttransistor (NMOSFET). The power amplifier may be configured to operateat a first level during transmit modes and operate at a second levelduring non-transmit modes. In some embodiments, the n-bit current sourcebank is configured to set reference current levels for without feedbackloops. The one or more temperature regions may include 2^(n)+2temperature regions.

For purposes of summarizing the disclosure, certain aspects, advantagesand novel features of the inventions have been described herein. It isto be understood that not necessarily all such advantages may beachieved in accordance with any particular embodiment of the invention.Thus, the invention may be embodied or carried out in a manner thatachieves or optimizes one advantage or group of advantages as taughtherein without necessarily achieving other advantages as may be taughtor suggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a block diagram of a monolithic integrated SOI CMOS radiofrequency front-end module having one or more features as describedherein.

FIG. 2 depicts a block diagram of a bias voltage generator of a poweramplifier having one or more features as described herein.

FIG. 3 depicts a block diagram of a biasing scheme for a monolithicintegrated SOI CMOS high-power amplifier for providing superiorsmall-signal gain flatness having one or more features as describedherein.

FIG. 4 depicts a schematic diagram of a wide linear-range PTAT-basedjunction temperature sensor having one or more features as describedherein.

FIG. 5 depicts a schematic diagram of an n-bit ADC having one or morefeatures as described herein.

FIG. 6 depicts a schematic diagram of a current source having one ormore features as described herein.

FIG. 7 shows a comparison of various n-bit reference currents to anon-linear (e.g., theoretical or target) current in accordance with someembodiments.

FIG. 8 illustrates a comparison graph of various n-bit current slopescompared to a target curve representing 0 dB gain flatness in accordancewith some embodiments.

FIG. 9 shows a comparison graph of a target n-bit current slope to ahigher-order temperature-compensated reference current in accordancewith some embodiments.

FIG. 10 shows reference currents providing less than 0.25 dB gainflatness from −40 to 125° C. for various n-bit PTAT devices inaccordance with some embodiments.

FIG. 11 shows a module including some or all of a front-end architecturehaving one or more features as described herein.

FIG. 12 depicts an example wireless device having one or moreadvantageous features described herein.

DESCRIPTION

The headings provided herein, if any, are for convenience only and donot necessarily affect the scope or meaning of the claimed invention.

Some high-performance, highly-integrated radio frequency front-endmodules designed for high-power Industrial, Scientific, Medical (ISM)band applications operate in the 860 to 930 MHz frequency range. Tosupport such designs, a radio frequency front-end module may integrate apower amplifier with relatively high output power (e.g., +22 dBm), arelatively low loss (e.g., less than 1.0 dB) and/or low power transmitbypass path (e.g., a radio frequency switch and/or antenna switch),and/or a low-noise amplifier (LNA) (e.g., having a noise figure ofapproximately 1.5 dB) into a single Silicon-On-Insulator (SOI)complementary metal-oxide-semiconductor (CMOS) die. Integrating suchdesigns on a single semiconductor die can support wide-band operationsand/or single-ended (e.g., 50Ω) transmit/receive radio frequencyinterfaces.

High-performance front-end modules may provide and/or require a varietyof specifications, which may include, among others: wide-supply voltageranges (e.g., 2.0 V to 5 V) and/or temperature ranges (e.g., −40° C. to125° C.); digital controls compatible with various CMOS levels (e.g.,1.2 V to 5 V); relatively fast turn-on/turn-off times (e.g., less than 5μSec); relatively low transmit bypass path loss (e.g., less than 1.0dB); a relatively low transmit bypass path current (e.g., less than 10μA); relatively low sleep-mode current (e.g., less than 1 μA);relatively high power amplifier output power (e.g., greater than 22 dBm)and/or superior gain flatness (e.g., less than 1 dB from −40° C. to 125°C.); relatively low quiescent current variation over PVT; and/orrelatively small die area consumption (e.g., less than 1.5 mm²).

To meet the above specifications, various modules and/or systemsdescribed herein may be configured to provide a radio frequencyfront-end module architecture configured to perform a variety offunctions. In one use case, a front-end module architecture may beconfigured to provide a high-quality noise-insensitive and/or radiofrequency coupling-insensitive bandgap voltage reference and/or a veryrobust low-dropout (LDO) voltage regulator (e.g., operating in a 2.0 Vto 5.0 V supply voltage range) with loading current (e.g., from sub-μAto approximately 200 mA) to support transmit modes (e.g., 25 mA to 180mA), receive modes (e.g., 5 mA to 40 mA), bypass modes (e.g., less than10 μA), and/or sleep modes (e.g., less than 1 μA). Moreover, the bandgapvoltage and/or LDO voltage may be configured to startup and/or shut downrelatively quickly during mode transition.

In another use case, a front-end module architecture may be configuredto provide a low-power (e.g., less than 100 nA) and/or less-regulatedsupply for a control logic decoder, level slicer, and/or levelconvertors to support digital control logic compatibility with variousCMOS levels (e.g., 1.2 V to 5 V). The block may be configured to beconstantly maintained in an awake state (e.g., greater than 1 μA).

Some embodiments herein may be configured to provide low-loss (e.g.,less than 1 dB) and/or fast turn-on/turn-off time transmit bypass paths,which may include RF switch(es) and/or antenna switch(es) powered by anLDO voltage. Some embodiments may utilize high-performance and/orlow-voltage SOI technology to establish a tradeoff between powerhandling and switching speed. Low-power circuitry may be used to supportlow-power (e.g., less than 10 μA) transmit bypass modes. Someembodiments may be configured to allow low-insertion loss switch(es)and/or control logic level convertors to operate under LDO overrelatively wide supply voltage ranges. In one use case, a sum of adirect current (DC) value from a bandgap (e.g., LDO) voltage and/or aleakage current from control logic level convertors and/or switches maybe limited within 10 μA without sacrificing startup time from sleep modeto other active modes.

Some embodiments may be configured to support relatively low sleepcurrents (e.g., less than 1 μA) by providing for shutting downhigh-power radio frequency blocks (e.g., power amplifier and LNA),bandgap, and/or LDO to improve system efficiency. Moreover, someembodiments may involve confining current consumption of various blocks(e.g., always-alive blocks, including switches, less-regulated supplies,control logic decoders, level slicers, and level convertors) and/orleakage current from output stages of the power amplifier which may bepowered by battery and/or external power supply directly within, forexample, 1 μA.

In some embodiments, an on-die power amplifier (e.g., an SOI CMOS poweramplifier) may be configured to provide relatively high output power(e.g., greater than 22 dBm) and/or may be configured to operate reliablyover relatively wide supply voltage ranges. Some embodiments may utilizerelatively large amplifiers (e.g., n-channel metal-oxide field-effecttransistors (NMOSFETs)) to provide relatively high current handling,relatively high voltage handling (e.g., through use of stacked amplifiertopology), relatively high power amplifier efficiency (e.g., throughbiasing), superior gain flatness (e.g., less than 1 dB) over frequencybands and/or wide-operating temperature ranges (e.g., −40° C. to 125°C.), relatively low power-down leakage current, and/or relatively highshut-down mode reliability. Moreover, some modules and/or systems may beconfigured to provide fast turn-on/turn-off of various components (e.g.,an LNA and/or power amplifier). Because there is a tradeoff betweenturn-on/turn-off times, leakage current, and die area, some embodimentsmay be configured for use with limited die area.

Usage of bandgap voltage references and/or LDO regulators may consumelarge die area and extensive resources (e.g., tens of μA of DC current).For example, bandgap voltage references and/or LDO regulators may berequired to turn off in sleep mode, however a power-down signal may bedifficult to generate without a power-down pin. Moreover, the power-downsignal may not be easily controlled if the supply voltage varies (e.g.,from 2 V to 5 V). However, because supply voltage levels from voltagedividers may be less regulated, controllers using simple voltagedividers may suffer from poor power supply rejection ratio (PSRR) and/orsupply voltage-dependent output voltage and may be limited to relativelynarrow supply voltage range applications. Some embodiments describedherein may advantageously support wide power supply ranges (e.g., 2 V to5 V) with reasonable PSRR. Embodiments may further provide lowsleep-mode current specifications by implementing a low leakage current(e.g., less than 100 nA) LDO regulator that may be configured to beturned off in sleep mode.

Maintaining controllers at always-alive levels when no externalpower-down pin is available may require all blocks within a radiofrequency front-end module to have a very low-power design. In somecases, it may be difficult or impossible to meet extremely low leakagecurrent specifications. Some embodiments described herein mayadvantageously involve generating a power-down signal from input controlsignals using a low DC current (e.g., less than 50 nA) mode detector topower down the bandgap voltage reference and/or LDO regulator (which maysupply current for all control signal path circuitry, an LNA, and/or afirst stage of the power amplifier). The mode detector may be configuredto be maintained in an always-alive state so that any operating modechanges can be detected quickly. Moreover, the mode detector may beconfigured to be powered by a low-power (e.g., less than 50 nA)less-regulated supply generator, which may advantageously be configuredto be maintained in an always-alive state.

Moreover, to provide well-regulated supply levels for level shiftersand/or logic decoders, various components may be implemented. Forexample, radio frequency switches, antenna switches, and/orhigh-threshold voltage devices (e.g., 5 V bulk CMOS and/or 5 Vsilicon-germanium (SiGe) bipolar junction CMOS (BiCMOS) processes) maybe used to reduce leakage current, simplify level convertor design,remove one or more level clippers, and/or increase reliability over awide supply range. However, such solutions may require multiple dies andmay result in higher cost and design complexity. Some embodimentsdescribed herein may advantageously be configured to implement alow-power bandgap voltage reference to provide a reference voltage(e.g., approximately 0.835 V) to an LDO regulator and/or poweramplifier. The low-power bandgap voltage reference may further provideLNA reference current generators, which may be configured to operatewell over wide-supply voltage ranges (e.g., 2 V to 5 V) and/or may beconfigured to be shut down in sleep mode with low leakage current (e.g.,less than 200 nA).

To achieve efficient radio frequency performance, a power amplifier maybe implemented in an SiGe BiCMOS and/or a gallium arsenide (GaAs)heterojunction bipolar transistor (HBT) using a proportional to absolutetemperature (PTAT) reference current, a complementary to absolutetemperature (CTAT) reference current, and/or a combination (e.g.,PTAT+/−CTAT) reference current generator for sufficiently small signalgain flatness. However, such designs may be relatively expensive.Moreover, multi-die solutions may result in greater die area, morecomplex die-to-die connections and/or packaging, and/or difficulttop-level simulation, each of which may cause increased cost and/ordesign complexity. Some embodiments described herein advantageouslyprovide reliable DC bias and/or gain flatness (e.g., less than 1 dB)over wide temperature ranges (e.g., −40° C. to 125° C.) for a CMOS poweramplifier. Moreover, some embodiments may be configured to provide abias network with a superior small-signal gain temperature compensationscheme utilizing on-die junction temperature sensors, n-bitanalog-to-digital convertors, and/or n-bit PTAT current source banks toset proper reference current levels for various operating temperatureregions (e.g., 2^(n)+2 regions) automatically without undesiredelectrical feedback loops. In this way, the power amplifier may beconfigured to operate with relatively high power-added efficiency (PAE)and/or superior gain flatness in transmit modes and/or relatively lowleakage current and/or high reliability when the power amplifier isdisabled.

Some embodiments provide modules and/or systems involving poweramplifier biasing schemes utilizing higher-order temperaturecompensation, junction temperature sensing, and/or automatic operatingtemperature region selection. Such biasing schemes may be configured toprovide effective gain flatness over wide operating temperature ranges(e.g., −40° C. to 125° C.). Some embodiments may involve on-die junctiontemperature sensors, n-bit analog-to-digital convertors, and/or n-bitPTAT current source banks to set proper reference current levels forvarious operating temperature regions (e.g., 2^(n)+2 regions)automatically without undesired electrical feedback loops. Moreover,some embodiments may involve a hybrid bias current topology of constantcurrent generators (e.g., proportional to square of temperature (PTAT2)or similar generators), which may be configured to generate largequiescent current variation over process, voltage, and temperature(PVT).

FIG. 1 depicts a block diagram of a monolithic integrated SOI CMOS radiofrequency front-end module 100 having one or more features as describedherein. In some embodiments, the front-end module 100 may be powered byan on-die LDO regulator 102 for wide-supply voltage compliance andsufficient PSRR for analog functional blocks. A voltage level clippermay be built into a logic level slicer 106 that may be configured toconvert various standard logic levels (e.g., CMOS, transistor-transistorlogic (TTL), low-voltage differential signaling (LVDS), current-modelogic (CML), low-voltage positive emitter-coupled logic (LVPECL), etc.)from 1.2 V to 5 V into a single 1.5 V logic level for wide logic levelcompliance. A reference voltage (“Vref”) generator 108 may be configuredto provide a regulated supply voltage (e.g., approximately 1.5 V) fordigital blocks (which may include a mode detector 110, voltage levelclipper, and/or logic level slicer 106) and may be configured to bemaintained in an always-alive state. The front-end module 100 mayfurther comprise a bandgap voltage (Vbg) generator 104. In someembodiments, the reference voltage generator 108, Vbg generator 104,and/or LDO regulator 102 may be configured to provide a clean referencevoltage (e.g., a Vbg of approximately 0.835 V) and a well-regulatedinternal supply regulated voltage (“Vreg”) for control logic decoders,logic level convertors, bias current/voltage generators for one or moreLNAs 114, radio frequency switches, and first stage power amplifiers. Aconstant reference current generator may be used for LNA biasing. Avarying slope (e.g., varying with temperature) reference current may beused for a 2-stage power amplifier 112 to achieve sub-1 dB gainflatness. The LNA, power amplifier, radio frequency switches, and/orvarious functional analog/digital blocks may be monolithicallyintegrated into a single SOI die.

A varying number of temperature regions may be used, which may affectgain flatness. For example, as the number of temperature regionsincreases (and the sizes of the temperature regions decrease), theoverall gain flatness may increase. The current slope may be designed toachieve overall gain flatness and/or increase flatness in the middle ofa temperature region. If only one current slope is used, gain values inthe middle of one or more temperature regions may be relatively flat.

In some embodiments, the number of temperature regions may beproportional with the number of bits. For example, the number oftemperature regions may be calculated using the equation 2^(n)+2, where“n” is the number of bits. To maintain high digital-to-analog converteraccuracy, the number of bits may be maintained below a threshold value.For example, only three bits or fewer may be used.

FIG. 2 depicts a block diagram of a bias voltage generator 200 of apower amplifier having one or more features as described herein. In someembodiments, the bias voltage generator 200 may comprise a second stageof the power amplifier. The bias voltage generator 200 may include amulti-stacked topology (e.g., a three-stack topology) that may be usedfor a power amplifier output stage. The output stage may be powered by avoltage source (“Vdd”) 210 (e.g., in the range of 2 V to 5 V). Somefield-effect transistors may have a relatively low nominal operatingvoltage (e.g., approximately 2.5 V, and/or a maximum of 2.75 V).Accordingly, the reliability for both on and off states of the poweramplifier may be critical. The bias voltage generator includes a firstresistor (“R21”) 221, a second resistor (“R22”) 222, a third resistor(“R31”) 231, and a fourth resistor (“R32”) 232.

When the power amplifier is turned on, an operational amplifier (OpAmp)205, together with a replica of the power amplifier output stage, mayset a first bias voltage (“VG_CS1”) for a first field-effect transistor(FET) 202 to be approximately equal to an output voltage of the OpAmp205. A second FET 204 in the output stage may be configured to provide asecond bias voltage (“VG_CS2”) that may be calculated as follows:VG_CS2=Vreg*R21/(R21+R22)+VG_CS1*R22/(R21+R22). A third FET 206 may beconfigured to be biased at a third bias voltage (“VG_CS3”), which may becalculated as follows: VG_CS3=VDD*R31/(R31+R32)+Vreg*R32/(R31+R32),where VDD 210 is the supply voltage. When the power amplifier is turnedoff, the first bias voltage may be approximately 0 V, the second biasvoltage may be equal to VDD−3*Vth,diode−Ileak*Rb1 (where “Vth,diode” isa diode forward conduction voltage and “Ileak” is leakage current), andthe third bias voltage may be equal to VDD 210. Any high voltage showsin the drain of the third FET 206 may be divided by stacked FETs suchthat all FETs in the power amplifier output stage may be protected fromhigh voltage stress in both on and off modes of the power amplifier.

The bias voltage generator 200 shown in FIG. 2 may have a cascodestructure and/or may be configured to provide multiple voltage outputlevels. In some embodiments, a first voltage level provided by the biasvoltage generator 200 may be configured to be used during active (i.e.,awake) states and a second voltage level may be used during sleep modes.The second voltage level may be relatively low (e.g., less than 1 V). Inthis way, the power amplifier may be configured to support a highcurrent mirror ratio and/or may be configured to generate a relativelyhigh yield.

FIG. 3 depicts a block diagram of a biasing scheme 300 for a monolithicintegrated SOI CMOS high-power amplifier for providing superiorsmall-signal gain flatness having one or more features as describedherein. In some embodiments, the biasing scheme 300 may comprise threemajor blocks: a junction temperature (Tj) sensor 302 configured todetect the power amplifier Tj and/or convert the Tj value to an outputvoltage (“Vtempsensor”) value; an n-bit analog-to-digital converter(ADC) 304 configured to convert the output voltage signal from the Tjsensor 302 into digital bits (e.g., n bits); and an n-bit current source306 (e.g., a p-channel FET (PFET) current source) controlled by ADC 304output digital bits to generate desired discrete reference currentlevels for specific Tj regions (e.g., 2^(n)+2 regions).

The generated voltage may be configured to increase with increasedjunction temperature. In some embodiments, once a certain temperaturelevel is reached (e.g., 50° C.), a signal indicated by the bits maychange and/or a different circuit path may be activated.

FIG. 4 depicts a schematic diagram of a wide linear-range PTAT-basedjunction temperature sensor 400 having one or more features as describedherein. In some embodiments, the sensor 400 may be incorporated in anSOI CMOS power amplifier die (e.g., the front-end module 100 of FIG. 1). The sensor 400 may comprise a bandgap-core configured to generate acurrent (“Iptat”) and/or a biasing gate voltage (“Vptat_pfet”) to drivean n-bit ADC-controlled PFET current source. A bandgap voltage-basedvoltage-to-current converter (V2I) may be used to generate a constantcurrent (e.g., a CTAT current (“ICTAT”)), which may broaden the linearrange of the sensor 400 operating temperature and/or voltage range.

FIG. 5 depicts a schematic diagram of an n-bit ADC 500 having one ormore features as described herein. The ADC 500 may be configured toutilize wide-input range OpAmp-based comparators with optimizedhysteresis. In some embodiments, the ADC 500 may be configured toconvert a junction temperature sensor (e.g., the sensor 400 in FIG. 4 )output voltage (e.g., Vptat) into digital bits. For example, the ADC 500may be configured to convert an output voltage into 2^(n) digital bits(e.g., B[0], B[1], up to B[2n−1]). The ADC 500 may be further configuredto generate one or more reference voltages (e.g., Vref_0, Vref_1 . . .Vref_n) using one or more resistor-based voltage dividers. In someembodiments, the ADC 500 may be configured to be powered by ahigh-quality LDO regulator and/or may comprise well-matchedpoly-resistor unit cells. Accordingly, PVT variations of referencevoltages for the ADC 500 may be negligible. Moreover, the ADC 500 may beconfigured to build a comparator bank 502 using a wide-input rangeand/or high-gain OpAmp together with a well-matched poly-resistorfeedback network. Accordingly, PVT variations and/or mismatches may beminimized as much as possible.

FIG. 6 depicts a schematic diagram of a current source 600 having one ormore features as described herein. The current source 600 may beconfigured to generate a reference current (“Iref_BiasPA”) and/or biascurrent for a power amplifier. For example, the current source 600 maybe configured to generate a reference current and/or a bias current fora first and/or second stage of a power amplifier. In some embodiments,the current source 600 may comprise an n-bit ADC-controlled PFET currentsource bank and/or may be configured to generate the reference currentfor an SOI CMOS power amplifier to achieve superior small-signal gainflatness. The current source 600 may comprise one or more currentmirrors 602.

In some embodiments, a reference current for an SOI CMOS power amplifiermay be a constant value. Such constant reference currents may be easierto design than non-linear current slopes and/or may be configured toprovide very low quiescent collector current (14 PVT variations, higheryield, and/or greater reliability. FIG. 7 shows a comparison of variousn-bit reference currents to a non-linear (e.g., theoretical or target)current. The more bits that are used, the closer a current slope can getto the target non-linear current slope. In some embodiments, anon-linear current slope may provide 0 dB variation. The referencecurrent may be calculated as follows: I_(ref)=I_(ctat)+I_(ptat) ^(x).I_(ptat) ^(x) may be calculated as follows: I_(ptat)^(x)=I₀+I₁(T_(j))+I₂(T_(j) ²)+ . . . +I_(n)(T_(j) ^(n)).

FIG. 8 illustrates a comparison graph of various n-bit current slopescompared to a target curve representing 0 dB gain flatness. Currentslopes may be improved using the following formula:I_(ref)=M×I_(ptat)−I_(ctat), which may provide a wider Tj sensoroperating range. A curve may become more flat with a smaller number ofbits.

FIG. 9 shows a comparison graph of a target n-bit current slope to ahigher-order temperature-compensated reference current. In someembodiments, a reference current using a very small bit value ADC caneffectively trace the target curve in each temperature region. Theoverall peak value of the curve may result in relatively high gainflatness in the center of each temperature region, as well as arelatively high overall gain flatness.

FIG. 10 shows reference currents providing less than 0.25 dB gainflatness from −40 to 125° C. for various n-bit PTAT devices. In someembodiments, a 1-bit junction temperature sharper-slope voltagereference may be used.

In some embodiments, a front-end module having one or more features asdescribed herein can be implemented in different products, includingthose examples provided herein. Such products can include, or beassociated with, any front-end system or module in which poweramplification is desired. Such a front-end module or system can beconfigured to support wireless operations involving, for example,cellular devices, WLAN devices, IoT devices, etc.

FIG. 11 shows that in some embodiments, some or all of a front-endarchitecture having one or more features as described herein can beimplemented in a module. Such a module can be, for example, a front-endmodule (FEM). In the example of FIG. 11 , a module 1110 can include apackaging substrate 1112, and a number of components can be mounted onsuch a packaging substrate. For example, a control component 1102, apower amplifier assembly 1104, an antenna tuner component 1106, and aduplexer assembly 1108 can be mounted and/or implemented on and/orwithin the packaging substrate 1112. Other components such as a numberof SMT devices 1104 and an antenna switch module (ASM) 1116 can also bemounted on the packaging substrate 1112. Although all of the variouscomponents are depicted as being laid out on the packaging substrate1112, it will be understood that some component(s) can be implementedover other component(s).

In some implementations, a device and/or a circuit having one or morefeatures described herein can be included in an RF device such as awireless device. Such a device and/or a circuit can be implementeddirectly in the wireless device, in a modular form as described herein,or in some combination thereof. In some embodiments, such a wirelessdevice can include, for example, a cellular phone, a smart-phone, ahand-held wireless device with or without phone functionality, awireless tablet, etc.

FIG. 12 depicts an example wireless device 1200 having one or moreadvantageous features described herein. In the context of a modulehaving one or more features as described herein, such a module can begenerally depicted by a dashed box 1210, and can be implemented as, forexample, a front-end module (FEM).

Referring to FIG. 12 , power amplifiers 1220 can receive theirrespective RF signals from a transceiver 1209 that can be configured andoperated in known manners to generate RF signals to be amplified andtransmitted, and to process received signals. The transceiver 1209 isshown to interact with a baseband sub-system 1208 that is configured toprovide conversion between data and/or voice signals suitable for a userand RF signals suitable for the transceiver 1209. The transceiver 1209can also be in communication with a power management component 1216 thatis configured to manage power for the operation of the wireless device1200. Such power management can also control operations of the basebandsub-system 1208 and the module 1210.

The baseband sub-system 1208 is shown to be connected to a userinterface 1202 to facilitate various input and output of voice and/ordata provided to and received from the user. The baseband sub-system1208 can also be connected to a memory 1204 that is configured to storedata and/or instructions to facilitate the operation of the wirelessdevice, and/or to provide storage of information for the user.

In the example wireless device 1200, outputs of the PAs 1220 are shownto be routed to their respective duplexers 1220. Such amplified andfiltered signals can be routed to an antenna 1218 through an antennaswitch 1214 for transmission. In some embodiments, the duplexers 1220can allow transmit and receive operations to be performed simultaneouslyusing a common antenna (e.g., 1218). In FIG. 12 , received signals areshown to be routed to “Rx” paths (not shown) that can include, forexample, a low-noise amplifier (LNA).

As described herein, one or more features of the present disclosure canprovide a number of advantages when implemented in systems such as thoseinvolving the wireless device of FIG. 12 . For example, a controller1212, which may or may not be part of the module 1210, can monitor basecurrents associated with at least some of the power amplifiers 1220.Based on such monitored base currents, an antenna tuner 1206 (which mayor may not be part of the module 1210), can be adjusted to provide adesired impedance to the corresponding power amplifier.

The present disclosure describes various features, no single one ofwhich is solely responsible for the benefits described herein. It willbe understood that various features described herein may be combined,modified, or omitted, as would be apparent to one of ordinary skill.Other combinations and sub-combinations than those specificallydescribed herein will be apparent to one of ordinary skill, and areintended to form a part of this disclosure. Various methods aredescribed herein in connection with various flowchart steps and/orphases. It will be understood that in many cases, certain steps and/orphases may be combined together such that multiple steps and/or phasesshown in the flowcharts can be performed as a single step and/or phase.Also, certain steps and/or phases can be broken into additionalsub-components to be performed separately. In some instances, the orderof the steps and/or phases can be rearranged and certain steps and/orphases may be omitted entirely. Also, the methods described herein areto be understood to be open-ended, such that additional steps and/orphases to those shown and described herein can also be performed.

Some aspects of the systems and methods described herein canadvantageously be implemented using, for example, computer software,hardware, firmware, or any combination of computer software, hardware,and firmware. Computer software can comprise computer executable codestored in a computer readable medium (e.g., non-transitory computerreadable medium) that, when executed, performs the functions describedherein. In some embodiments, computer-executable code is executed by oneor more general purpose computer processors. A skilled artisan willappreciate, in light of this disclosure, that any feature or functionthat can be implemented using software to be executed on a generalpurpose computer can also be implemented using a different combinationof hardware, software, or firmware. For example, such a module can beimplemented completely in hardware using a combination of integratedcircuits. Alternatively or additionally, such a feature or function canbe implemented completely or partially using specialized computersdesigned to perform the particular functions described herein ratherthan by general purpose computers.

Multiple distributed computing devices can be substituted for any onecomputing device described herein. In such distributed embodiments, thefunctions of the one computing device are distributed (e.g., over anetwork) such that some functions are performed on each of thedistributed computing devices.

Some embodiments may be described with reference to equations,algorithms, and/or flowchart illustrations. These methods may beimplemented using computer program instructions executable on one ormore computers. These methods may also be implemented as computerprogram products either separately, or as a component of an apparatus orsystem. In this regard, each equation, algorithm, block, or step of aflowchart, and combinations thereof, may be implemented by hardware,firmware, and/or software including one or more computer programinstructions embodied in computer-readable program code logic. As willbe appreciated, any such computer program instructions may be loadedonto one or more computers, including without limitation a generalpurpose computer or special purpose computer, or other programmableprocessing apparatus to produce a machine, such that the computerprogram instructions which execute on the computer(s) or otherprogrammable processing device(s) implement the functions specified inthe equations, algorithms, and/or flowcharts. It will also be understoodthat each equation, algorithm, and/or block in flowchart illustrations,and combinations thereof, may be implemented by special purposehardware-based computer systems which perform the specified functions orsteps, or combinations of special purpose hardware and computer-readableprogram code logic means.

Furthermore, computer program instructions, such as embodied incomputer-readable program code logic, may also be stored in a computerreadable memory (e.g., a non-transitory computer readable medium) thatcan direct one or more computers or other programmable processingdevices to function in a particular manner, such that the instructionsstored in the computer-readable memory implement the function(s)specified in the block(s) of the flowchart(s). The computer programinstructions may also be loaded onto one or more computers or otherprogrammable computing devices to cause a series of operational steps tobe performed on the one or more computers or other programmablecomputing devices to produce a computer-implemented process such thatthe instructions which execute on the computer or other programmableprocessing apparatus provide steps for implementing the functionsspecified in the equation(s), algorithm(s), and/or block(s) of theflowchart(s).

Some or all of the methods and tasks described herein may be performedand fully automated by a computer system. The computer system may, insome cases, include multiple distinct computers or computing devices(e.g., physical servers, workstations, storage arrays, etc.) thatcommunicate and interoperate over a network to perform the describedfunctions. Each such computing device typically includes a processor (ormultiple processors) that executes program instructions or modulesstored in a memory or other non-transitory computer-readable storagemedium or device. The various functions disclosed herein may be embodiedin such program instructions, although some or all of the disclosedfunctions may alternatively be implemented in application-specificcircuitry (e.g., ASICs or FPGAs) of the computer system. Where thecomputer system includes multiple computing devices, these devices may,but need not, be co-located. The results of the disclosed methods andtasks may be persistently stored by transforming physical storagedevices, such as solid state memory chips and/or magnetic disks, into adifferent state.

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense, as opposed to anexclusive or exhaustive sense; that is to say, in the sense of“including, but not limited to.” The word “coupled”, as generally usedherein, refers to two or more elements that may be either directlyconnected, or connected by way of one or more intermediate elements.Additionally, the words “herein,” “above,” “below,” and words of similarimport, when used in this application, shall refer to this applicationas a whole and not to any particular portions of this application. Wherethe context permits, words in the above Detailed Description using thesingular or plural number may also include the plural or singular numberrespectively. The word “or” in reference to a list of two or more items,that word covers all of the following interpretations of the word: anyof the items in the list, all of the items in the list, and anycombination of the items in the list. The word “exemplary” is usedexclusively herein to mean “serving as an example, instance, orillustration.” Any implementation described herein as “exemplary” is notnecessarily to be construed as preferred or advantageous over otherimplementations.

The disclosure is not intended to be limited to the implementationsshown herein. Various modifications to the implementations described inthis disclosure may be readily apparent to those skilled in the art, andthe generic principles defined herein may be applied to otherimplementations without departing from the spirit or scope of thisdisclosure. The teachings of the invention provided herein can beapplied to other methods and systems, and are not limited to the methodsand systems described above, and elements and acts of the variousembodiments described above can be combined to provide furtherembodiments. Accordingly, the novel methods and systems described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the methods andsystems described herein may be made without departing from the spiritof the disclosure. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the disclosure.

What is claimed is:
 1. A biasing method for a power amplifier, themethod comprising: detecting a junction temperature of the poweramplifier; generating an output voltage based at least in part on thedetected junction temperature; converting the output voltage intodigital bits; and automatically setting reference current levels for oneor more operating temperature regions based at least in part on thedigital bits.
 2. The method of claim 1 wherein the output voltage isconfigured to increase with increased junction temperature.
 3. Themethod of claim 1 further comprising activating a circuit path inresponse to the junction temperature exceeding a threshold value.
 4. Themethod of claim 1 wherein the output voltage is converted into n digitalbits, and wherein the method further comprises setting reference currentlevels for 2^(n)+2 temperature regions.
 5. The method of claim 1wherein: the junction temperature is detected at a junction temperaturesensor; the output voltage is converted into digital bits at ananalog-to-digital converter; the reference current levels areautomatically set at a current source bank; and the junction temperaturesensor, analog-to-digital converter, and current source bank integratedon a first semiconductor die.
 6. The method of claim 5 wherein the firstsemiconductor die further comprises the power amplifier.
 7. The methodof claim 5 wherein the first semiconductor die further comprises a biasnetwork including a current mirror.
 8. The method of claim 1 wherein thereference current levels are set without feedback loops.
 9. Asemiconductor die comprising: a power amplifier; a junction temperaturesensor configured to detect a junction temperature of the poweramplifier and convert the junction temperature to an output voltage; ann-bit analog-to-digital converter configured to convert the outputvoltage into digital bits; and an n-bit current source bank configuredto automatically set reference current levels for one or more operatingtemperature regions.
 10. The semiconductor die of claim 9 wherein theoutput voltage is configured to increase with increased junctiontemperature.
 11. The semiconductor die of claim 9 wherein the n-bitanalog-to-digital converter is configured to convert the output voltageinto n digital bits, and wherein the n-bit current source bank isconfigured to automatically set reference current levels for 2^(n)+2temperature regions.
 12. The semiconductor die of claim 9 wherein then-bit current source bank is configured to set reference current levelswithout feedback loops.
 13. The semiconductor die of claim 9 furthercomprising a bias network including a current mirror.
 14. Thesemiconductor die of claim 9 wherein the power amplifier is configuredto provide an output power of at least 22 dBm.
 15. A front-end modulecomprising: a power amplifier; a junction temperature sensor configuredto detect a junction temperature of the power amplifier and convert thejunction temperature to an output voltage; an n-bit analog-to-digitalconverter configured to convert the output voltage into digital bits;and an n-bit current source bank configured to automatically setreference current levels for one or more operating temperature regions.16. The front-end module of claim 15 wherein the output voltage isconfigured to increase with increased junction temperature.
 17. Thefront-end module of claim 15 wherein the n-bit analog-to-digitalconverter is configured to convert the output voltage into n digitalbits, and wherein the n-bit current source bank is configured toautomatically set reference current levels for 2^(n)+2 temperatureregions.
 18. The front-end module of claim 15 wherein the n-bit currentsource bank is configured to set reference current levels withoutfeedback loops.
 19. The front-end module of claim 15 wherein thejunction temperature sensor, n-bit analog-to-digital converter, n-bitcurrent source bank, and power amplifier are integrated on a firstsemiconductor die.
 20. The front-end module of claim 15 furthercomprising a bias network including a current mirror.